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| CA3146, CA3146A, CA3183, CA3183A TM Data Sheet April 2000 File Number 532.5 High-Voltage Transistor Arrays [ /Title (CA31 46, CA314 6A, CA318 3, CA318 3A) /Subject (HighVoltage Transistor Arrays ) /Autho r () /Keywords (Intersil Corporation, five, transistor array, low cost NPN, 40V, 50ma 75ma, mhz ft, high voltThe CA3146A, CA3146, CA3183A, and CA3183 are general purpose high voltage silicon NPN transistor arrays on a common monolithic substrate. Types CA3146A and CA3146 consist of five transistors with two of the transistors connected to form a differentially connected pair. These types are recommended for low power applications in the DC through VHF range. (CA3146A and CA3146 are high voltage versions of the popular predecessor type CA3046.) Types CA3183A and CA3183 consist of five high current transistors with independent connections for each transistor. In addition two of these transistors (Q1 and Q2) are matched at low current (i.e., 1mA) for applications where offset parameters are of special importance. A special substrate terminal is also included for greater flexibility in circuit design. (CA3183A and CA3183 are high voltage versions of the popular predecessor type CA3083.) The types with an "A" suffix are premium versions of their non-"A" counterparts and feature tighter control of breakdown voltages making them more suitable for higher voltage applications. For detailed application information, see companion Application Note AN5296 "Application of the CA3018 Integrated Circuit Transistor Array." Features * Matched General Purpose Transistors - VBE Match . . . . . . . . . . . . . . . . . . . . . . . . 5mV (Max) * Operation from DC to 120MHz (CA3146, CA3146A) * Low Noise Figure . . . . . . . . . . 3.2dB (CA3146, CA3146A) * High IC . . . . . . . . . . . . 75mA (Max) (CA3183, CA3183A) Applications * General Use in Signal Processing Systems in DC through VHF Range * Custom Designed Differential Amplifiers * Temperature Compensated Amplifiers * Lamp and Relay Drivers (CA3183, CA3183A) * Thyristor Firing (CA3183, CA3183A) Pinouts CA3146, CA3146A (PDIP, SOIC) TOP VIEW 1 Q5 2 DIFF. PAIR 3 4 Q2 Q4 Q1 14 13 SUBSTRATE 12 11 10 9 Q3 8 Ordering Information PART NUMBER (BRAND) CA3146AE CA3146AM (3146A) CA3146E CA3146M (3146) CA3146M96 (3146) CA3183AE CA3183AM96 (3183A) CA3183E CA3183M (3183) CA3183M96 (3183) TEMP. RANGE (oC) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 14 Ld PDIP 14 Ld SOIC 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC Tape and Reel 16 Ld PDIP 16 Ld SOIC Tape and Reel 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC Tape and Reel PKG. NO. E14.3 M14.15 E14.3 M14.15 M14.15 E16.3 M16.15 E16.3 5 6 7 CA3183, CA3183A (PDIP, SOIC) TOP VIEW 1 2 3 4 SUBSTRATE 5 Q2 Q5 Q1 16 15 14 13 12 11 Q4 Q3 8 9 10 M16.15 6 M16.15 7 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 CA3146, CA3146A, CA3183, CA3183A Absolute Maximum Ratings Collector-to-Emitter Voltage (VCEO) CA3146A, CA3183A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V CA3146, CA3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Collector-to-Base Voltage (VCBO) CA3146A, CA3183A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V CA3146, CA3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Collector-to-Substrate Voltage (VCIO, Note 1) CA3146A, CA3183A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V CA3146, CA3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Emitter to Base Voltage (VEBO) all types. . . . . . . . . . . . . . . . . . . . . 5V Collector Current CA3146A, CA3146 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA CA3183A, CA3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75mA Base Current (IB) - CA3183A, CA3183 . . . . . . . . . . . . . . . . . . . 20mA Thermal Information Thermal Resistance (Typical, Note 2) JA (oC/W) 14 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 100 14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 200 16 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 95 16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Power Dissipation (Any One Transistor, Note 3) CA3146A, CA3146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mW CA3183A, CA3183. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range (all types) . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The collector of each transistor is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative than any collector voltage in order to maintain isolation between transistors, and to provide for normal transistor action. To avoid undesired coupling between transistors, the substrate terminal should be maintained at either DC or signal (AC) ground. A suitable bypass capacitor can be used to establish a signal ground. 2. JA is measured with the component mounted on an evaluation PC board in free air. 3. Care must be taken to avoid exceeding the maximum junction temperature. Use the total power dissipation (all transistors) and thermal resistances to calculate the junction temperature. Electrical Specifications CA3146 Series TEST CONDITIONS TA = 25oC TYPICAL PERF. CURVE FIG. NO. CA3146 CA3146A PARAMETER SYMBOL MN TYP MAX MIN TYP MAX UNITS DC CHARACTERISTICS FOR EACH TRANSISTOR Collector-to-Base Breakdown Voltage Collector-to-Emitter Breakdown Voltage Collector-to-Substrate Breakdown Voltage Emitter-to-Base Breakdown Voltage Collector-Cutoff Current Collector-Cutoff Current DC Forward-Current Transfer Ratio V(BR)CBO IC = 10A, IE = 0 V(BR)CEO IC = 1mA, IB = 0 V(BR)CIO V(BR)EBO ICEO ICBO hFE ICI = 10A, IB = 0, IE = 0 IE = 10A, IC = 0 VCE = 10V, IB = 0 VCB = 10V, IE = 0 VCE = 5V, IC = 10mA VCE = 5V, IC = 1mA VCE = 5V, IC = 10A Base-to-Emitter Voltage Collector-to-Emitter Saturation Voltage VBE VCE SAT VCE = 3V, IC = 1mA IC = 10mA, IB = 1mA 1 2 3 3 3 4 5 40 30 40 5 30 0.63 72 56 72 7 See Curve 0.002 85 100 90 0.73 0.33 5 100 0.83 50 40 50 5 30 0.63 72 56 72 7 See Curve 0.002 85 100 90 0.73 0.33 5 100 0.83 V V V V A nA V V DC CHARACTERISTICS FOR TRANSISTORS Q1 AND Q2 (As A Differential Amplifier) Magnitude of Input Offset Voltage |VBE1 - VBE2| Magnitude of Base-to-Emitter Temperature Coefficient |VIO| V BE --------------T VCE = 5V, IE = 1mA VCE = 5V, IE = 1mA 6, 7 0.48 1.9 5 0.48 1.9 5 mV mV/oC 2 CA3146, CA3146A, CA3183, CA3183A Electrical Specifications CA3146 Series (Continued) TEST CONDITIONS TA = 25oC VCE = 5V, IC1 = IC2 = 1mA VCE = 5V, IC1 = IC2 = 1mA TYPICAL PERF. CURVE FIG. NO. CA3146 CA3146A PARAMETER Magnitude of VIO (VBE1 - VBE2) Temperature Coefficient Magnitude of Input Offset Current |IIO1 - IIO2| (CA3146AE and CA3146E Only) DYNAMIC CHARACTERISTICS Low Frequency Noise Figure SYMBOL V IO ------------T IIO MN - TYP 1.1 MAX - MIN - TYP 1.1 MAX - UNITS V/oC 8 - 0.3 2 - 0.3 2 A NF f = 1kHz, VCE = 5V, IC = 100A, Source Resistance = 1k 10 - 3.25 - - 3.25 - dB Low-Frequency, Small-Signal Equivalent-Circuit Characteristics: Forward-Current Transfer Ratio Short-Circuit Input Impedance Open-Circuit Output Impedance Open-Circuit Reverse Voltage Transfer Ratio Admittance Characteristics: Forward Transfer Admittance Input Admittance Output Admittance Reverse Transfer Admittance Gain-Bandwidth Product Emitter-to-Base Capacitance Collector-to-Base Capacitance Collector-to-Substrate Capacitance YFE YIE YOE YRE fT CEB CCB CCl f = 1MHz, VCE = 5V, IC = 1 mA f = 1MHz, VCE = 5V, IC = 1 mA f = 1MHz, VCE = 5V, IC = 1 mA f = 1MHz, VCE = 5V, IC = 1 mA VCE = 5V, IC = 3mA VEB = 5V, IE = 0 VCB = 5V, IC = 0 VCl = 5V, IC = 0 13 14 15 16 17 18 18 18 300 31j1.5 0.3 + j0.04 0.001 + j0.03 See Curve 500 0.70 0.37 2.2 300 31-j1.5 0.35 + j0.04 0.001 + j0.03 See Curve 500 0.70 0.37 2.2 mS mS mS mS MHz pF pF pF hFE hIE hOE hRE f = 1kHz, VCE = 5V, IC = 1mA f = 1kHz, VCE = 5V, IC = 1mA f = 1kHz, VCE = 5V, IC = 1mA f = 1kHz, VCE = 5V, IC = 1mA 12 12 12 12 100 3.5 15.6 1.8 x 10-4 100 2.7 15.6 1.8 x 10-4 k S - Electrical Specifications CA3183 Series TEST CONDITIONS TA = 25oC IC = 100A, IE = 0 IC = 1mA, IB = 0 ICI = 100A, IB = 0, IE = 0 IE = 500A, IC = 0 VCE = 10V, IB = 0 TYPICAL PERF. CURVE FIG. NO. CA3183 CA3183A PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS DC CHARACTERISTICS FOR EACH TRANSISTOR Collector-to-Base Breakdown Voltage Collector-to-Emitter Breakdown Voltage Collector-to-Substrate Breakdown Voltage Emitter-to-Base Breakdown Voltage Collector-Cutoff Current V(BR)CBO V(BR)CEO V(BR)ClO V(BR)EBO ICEO 19 40 30 40 5 10 50 40 50 5 10 V V V V A 3 CA3146, CA3146A, CA3183, CA3183A Electrical Specifications CA3183 Series (Continued) TEST CONDITIONS TA = 25oC VCB = 10V, IE = 0 VCE = 3V, IC = 10mA VCE = 5V, IC = 50mA VBE VCE SAT (Note 3) VCE = 3V, IC = 10mA IC = 50mA, IB = 5mA TYPICAL PERF. CURVE FIG. NO. 20 21, 22 23 24 CA3183 CA3183A PARAMETER Collector-Cutoff Current DC Forward-Current Transfer Ratio Base-to-Emitter Voltage Collector-to-Emitter Saturation Voltage SYMBOL ICBO hFE MIN 40 40 0.65 - TYP 0.75 1.7 MAX 1 0.85 3.0 MIN 40 40 0.65 - TYP 0.75 1.7 MAX 1 0.85 3.0 UNITS A V V FOR TRANSISTORS Q1 AND Q2 (AS A DIFFERENTIAL AMPLIFIER) Absolute Input Offset Voltage Absolute Input Offset Current |VIO| |IIO| VCE = 3V, IC = 1mA VCE = 3V, IC = 1mA 25 26 0.47 0.78 5 2.5 0.47 0.78 5 2.5 mV A Typical Performance Curves 103 COLLECTOR CUTOFF CURRENT (nA) IB = 0 102 VCE = 10V 10 VCE = 5V 1 10-1 10-2 10-3 0 25 50 75 DC Characteristics - CA3146 Series 102 COLLECTOR CUTOFF CURRENT (nA) 10 1 10-1 10-2 10-3 10-4 0 25 50 75 TEMPERATURE (oC) 100 125 IE = 0 VCB = 15 VCB = 10 VCB = 5 100 125 TEMPERATURE (oC) FIGURE 1. ICEO vs TEMPERATURE FOR ANY TRANSISTOR FIGURE 2. ICBO vs TEMPERATURE FOR ANY TRANSISTOR DC FORWARD CURRENT TRANSFER RATIO 160 140 120 100 VCE = 5V TA = 125oC VCE = 5V BASE TO EMITTER VOLTAGE (V) 0.9 0.8 0.7 0.6 0.5 0.4 -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) IE = 1mA IE = 3mA 25oC 80 60 -55oC 40 20 0.01 0.1 1 10 COLLECTOR CURRENT (mA) FIGURE 3. hFE vs IC FOR ANY TRANSISTOR FIGURE 4. VBE vs TEMPERATURE FOR ANY TRANSISTOR 4 CA3146, CA3146A, CA3183, CA3183A Typical Performance Curves TA = 25oC 1.50 COLLECTOR TO EMITTER SATURATION VOLTAGE (V) 1.25 1.0 hFE = 10 0.75 0.50 0.25 OFFSET VOLTAGE (mV) DC Characteristics - CA3146 Series (Continued) 5 VCE = 5V 4 3 2 0.75 0.50 0.25 0 -75 IE = 0.1mA IE = 1mA IE = 10mA 0 10 20 30 40 -50 -25 0 25 50 75 100 125 COLLECTOR CURRENT (mA) TEMPERATURE (oC) FIGURE 5. VCE SAT vs IC FOR ANY TRANSISTOR FIGURE 6. VIO vs TEMPERATURE FOR Q1 AND Q2 BASE TO EMITTER VOLTAGE (V) VCE = 5V TA = 25oC 3 INPUT OFFSET VOLTAGE Q1 AND Q2 (mV) 0.8 10 INPUT OFFSET CURRENT (A) VCE = 5V TA = 25oC 0.7 1.0 0.6 2 0.1 0.5 |VBE1 - VBE2| 0.4 0.01 1 0 0.1 1.0 10 EMITTER CURRENT (mA) 0.01 0.01 0.1 1.0 10 COLLECTOR CURRENT (mA) FIGURE 7. VBE AND VIO vs IE FOR Q1 AND Q2 FIGURE 8. IIO vs IC FOR Q1 AND Q2 Typical Performance Curves VCE = 5V RS = 500 TA = 25oC Dynamic Characteristics (For Any Transistor) - CA3146 Series VCE = 5V RS = 1000 TA = 25oC 20 NOISE FIGURE (dB) 20 f = 0.1kHz f = 1kHz NOISE FIGURE (dB) 15 15 f = 0.1kHz f = 1kHz 10 f = 10kHz 5 10 f = 10kHz 5 0 0.01 0 0.1 COLLECTOR CURRENT (mA) 1.0 0.01 0.1 COLLECTOR CURRENT (mA) 1.0 FIGURE 9. NF vs IC AT RS = 500 FIGURE 10. NF vs IC AT RS = 1k 5 CA3146, CA3146A, CA3183, CA3183A Typical Performance Curves 30 25 NOISE FIGURE (dB) 20 15 10 5 NORMALIZED h PARAMETERS VCE = 5V RS = 10000 TA = 25oC f = 0.1kHz f = 1kHz f = 10kHz Dynamic Characteristics (For Any Transistor) - CA3146 Series (Continued) 100 VCE = 5V f = 1kHz TA = 25oC 10 hFE = 100 hIE = 2.7k hRE = 1.88 x 10-4 hOE = 15.6S hOE AT 1mA 1.0 hRE hFE 0 0.01 hIE 0.1 COLLECTOR CURRENT (mA) 1.0 0.1 0.01 0.1 1.0 10 COLLECTOR CURRENT (mA) FIGURE 11. NF vs IC AT RS = 10k FIGURE 12. hFE, hIE, hOE, hRE vs IC FORWARD TRANSFER CONDUCTANCE (gFE) OR SUSCEPTANCE (bFE) (mS) 40 30 20 10 0 -10 -20 COMMON EMITTER CIRCUIT, BASE INPUT TA = 25oC, VCE = 5V, IC = 1mA INPUT CONDUCTANCE (gIE) OR SUSCEPTANCE (bIE) (mS) 6 5 4 3 bIE COMMON EMITTER CIRCUIT, BASE INPUT TA = 25oC, VCE = 5V, IC = 1mA gFE 2 1 gIE 0 0.1 1.0 10 FREQUENCY (MHz) 100 bFE 0.1 1.0 10 FREQUENCY (MHz) 100 FIGURE 13. yFE vs FREQUENCY FIGURE 14. yIE vs FREQUENCY REVERSE TRANSFER CONDUCTANCE (gRE) OR SUSCEPTANCE (bRE) (mS) 6 OUTPUT CONDUCTANCE (gOE) OR SUSCEPTANCE (bOE) (mS) 5 4 3 2 1 COMMON EMITTER CIRCUIT, BASE INPUT TA = 25oC, VCE = 3V, IC = 1mA COMMON EMITTER CIRCUIT, BASE INPUT TA = 25oC, VCE = 5V, IC = 1mA gRE IS SMALL AT FREQUENCIES LESS THAN 500MHz bOE 0 -0.5 -1.0 bRE -1.5 -2.0 1 10 FREQUENCY (MHz) 100 gOE 0 0.1 1.0 10 FREQUENCY (MHz) 100 FIGURE 15. FIGURE 15. yOE vs FREQUENCY FIGURE 16. FIGURE 16. yRE vs FREQUENCY 6 CA3146, CA3146A, CA3183, CA3183A Typical Performance Curves VCE = 5V TA = 25oC Dynamic Characteristics (For Any Transistor) - CA3146 Series (Continued) TA = 25oC GAIN BANDWIDTH PRODUCT (MHz) 1000 900 800 700 4 CAPACITANCE (pF) 3 600 500 400 300 200 100 2 CCI CEB CCB 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 COLLECTOR CURRENT (mA) BIAS VOLTAGE (V) FIGURE 17. fT vs IC FIGURE 18. CEB, CCB, CCI vs BIAS VOLTAGE Typical Performance Curves COLLECTOR CUTOFF CURRENT (nA) 1 VCE = 10V DC Characteristics - CA3183 Series 10-1 COLLECTOR CUTOFF CURRENT (nA) VCB = 10V 10-1 10-2 10-2 10-3 10-3 10-4 -50 -25 0 25 50 75 100 10-4 -50 -25 0 25 50 75 100 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 19. ICEO vs TEMPERATURE FOR ANY TRANSISTOR FIGURE 20. ICBO vs TEMPERATURE FOR ANY TRANSISTOR VCE = 3V 100 125 DC FORWARD CURRENT TRANSFER RATIO (hFE) 100 75 50 25 0 -50 90 80 70 TA = 25oC VCE = 10V IC = 0.1mA IC = 1mA IC = 10mA DC FORWARD CURRENT TRANSFER RATIO (hFE) VCE = 3V 60 50 40 -25 0 25 50 75 100 0.1 1.0 10 TEMPERATURE (oC) COLLECTOR CURRENT (mA) FIGURE 21. hFE vs TEMPERATURE FOR ANY TRANSISTOR FIGURE 22. hFE vs IC FOR ANY TRANSISTOR 7 CA3146, CA3146A, CA3183, CA3183A Typical Performance Curves DC Characteristics - CA3183 Series (Continued) TA = 25oC hFE = 10 0.9 BASE TO EMITTER VOLTAGE (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.1 1.0 TA = 70oC TA = 25oC TA = 0oC 1.0 COLLECTOR TO EMITTER SATURATION VOLTAGE (V) 0.1 10 10 COLLECTOR CURRENT (mA) 100 COLLECTOR CURRENT (mA) FIGURE 23. VBE vs IC FOR ANY TRANSISTOR FIGURE 24. VCE SAT vs IC FOR ANY TRANSISTOR ABSOLUTE INPUT - OFFSET VOLTAGE (mV) ABSOLUTE INPUT - OFFSET CURRENT (A) VCE = 3V VCE = 3V TA = 25oC 1.0 TA = 25oC TA = 70oC TA = 0oC 1.0 0.1 0.1 1.0 COLLECTOR CURRENT (mA) 10 0.1 0.1 1.0 COLLECTOR CURRENT (mA) 10 FIGURE 25. |VIO| vs IC FOR DIFFERENTIAL AMPLIFIER (Q1 AND Q2) FIGURE 26. |IIO| vs IC FOR DIFFERENTIAL AMPLIFIER (Q1 AND Q2) 8 CA3146, CA3146A, CA3183, CA3183A Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E -C- eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 14 2.93 9 CA3146, CA3146A, CA3183, CA3183A Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A1 A2 -C- B B1 C D D1 E eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 2.54 BSC 7.62 BSC 2.93 16 10.92 3.81 10 CA3146, CA3146A, CA3183, CA3183A Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M14.15 (JEDEC MS-012-AB ISSUE C) 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574 A1 B C D E A1 0.10(0.004) C e B 0.25(0.010) M C AM BS e H h L N 0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27 NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 11 CA3146, CA3146A, CA3183, CA3183A Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 A1 B C D A1 0.10(0.004) C E e H h L N e B 0.25(0.010) M C AM BS 0.050 BSC 0.2284 0.0099 0.016 16 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27 NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 12 |
Price & Availability of CA3183
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